1. Field of the Invention
The present invention relates generally to semiconductor devices and methods of manufacturing the same, and more particularly to a semiconductor device having a semiconductor element mounted and resin-sealed on a wiring board in which vias are formed, and a method of manufacturing the same.
2. Description of the Related Art
There is a demand for reduction in the size and thickness of electronic components as electronic apparatuses have become smaller in size, higher in density, and higher in functionality. In response to this, surface mount packages including Ball Grid Array (BGA) are proposed as packages reduced in surface mount area by size reduction so as to be excellent for high-density mounting of semiconductor devices.
FIGS. 1A and 1B are diagrams showing the structure of a conventional semiconductor device. Specifically, FIG. 1A is a cross-sectional view of the semiconductor device, and FIG. 1B is an enlarged view of the part circled with a dotted line in FIG. 1A. In FIG. 1B, only one solder ball is graphically shown for convenience of description.
Referring to FIG. 1, a semiconductor device 10 has a structure where a semiconductor element 2 is mounted on one principal surface (upper surface) of a wiring board 1 with a die bonding material 3 such as a die bonding film interposed therebetween and multiple solder balls 4 formed mainly of solder and serving as external connection terminals such as spherical electrode terminals are provided in a grid-like manner on the other principal surface (lower surface) of the wiring board 1.
The semiconductor element 2 is formed by a known semiconductor manufacturing process using a silicon (Si) semiconductor substrate. External connection pads (whose graphical representation is omitted) to which bonding wires 5 formed of gold (Au) or the like are connected are provided on the upper surface of the semiconductor element 2. The semiconductor element 2 is electrically connected to the wiring board 1 through the bonding wires 5.
The upper side of the wiring board 1 is sealed with sealing resin 6 such as epoxy resin.
Thus, the semiconductor device 10 has the semiconductor element 2 packaged with the wiring board 1, the bonding wires 5, and the sealing resin 6 (into a module).
Here, a detailed description is given, with reference also to FIGS. 2A and 2B, of the structure of the wiring board 1. FIGS. 2A and 2B are diagrams showing the structure of the wiring board 1 of the semiconductor device 10 shown in FIGS. 1A and 1B. Specifically, FIG. 2A is a plan view of the wiring board 1, in which a graphical representation of a resist layer is omitted for convenience of description. FIG. 2B is a cross-sectional view of the wiring board 1 of FIG. 2A, taken along the line A-A.
The wiring board 1, which may also be referred to as an interposer, is a support board having a board base 7 formed of insulating resin such as glass epoxy resin, and a wiring (interconnect) layer 8A of copper (Cu) or the like provided on the surface (upper surface) of the board base 7.
The wiring layer 8A except a region to which the bonding wires 5 are connected is selectively covered with a resist layer 9A. That is, the resist pattern on the wiring board 1, on which the semiconductor device 2 is mounted, has a structure where part of the pattern where the wiring board 1 is electrically connected to the semiconductor element 2 by wire bonding is open while the other part is covered with the resist layer 9A.
A wiring (interconnect) layer 8B formed of copper (Cu) or the like is also provided at the other principal surface (lower surface) of the wiring board 1, and the wiring layer 8B is selectively covered with a resist layer 9B. That is, in the resist pattern on the lower surface of the wiring board 1, only parts corresponding to parts of the wiring layer 8B to serve as mounting terminals are open for electrical connection, and the solder balls 4 are provided on the parts of the wiring layer 8B exposed through the open parts of the resist pattern.
Vias 13 are formed inside the wiring board 1. In each via 13, a through hole is formed and a wiring (interconnect) part 11 is provided on the peripheral surface of the through hole. The entire through hole is plated so as to ensure the electrical continuity of the layers of the wiring board 1. The through hole is filled with via filling resin 12 such as epoxy resin. The wiring layer 8A and the wiring layer 8B, on which the solder balls 4 are provided, are connected through the vias 13.
Thus, the conventional semiconductor device 10 has a two-layer structure formed of the wiring board 1 and the sealing resin 6 provided on the wiring board 1 and containing the semiconductor element 2, etc. Further, the wiring board 1 of the semiconductor device 10 has a structure where the upper side of each via 13 filled with the via filling resin 12 is covered with the resist layer 9A.
Aside from the configuration shown in FIGS. 1A and 1B and FIGS. 2A and 2B, there is proposed a circuit board having an insulating layer, a via hole formed in the insulating layer and filled with a conductive material, and a wiring pattern formed on the surface of the insulating layer so as to be electrically connected to the conductive material, wherein a hole smaller in diameter than the via hole is formed at a position corresponding to the via hole in the wiring pattern so as to communicate with the via hole. (See Patent Document 1 listed below.)
Further, there is proposed a configuration where an increase in the adhesion between a wiring board and sealing resin is designed in the wiring board on which a semiconductor element is mounted by flip-chip bonding by forming a dummy via not to be filled with conductive paste in a region where the semiconductor element is to be mounted and filling the dummy via with the sealing resin. (See Patent Document 2 listed below.)
[Patent Document 1] Japanese Laid-Open Patent Application No. 9-82835
[Patent Document 2] Japanese Laid-Open Patent Application No. 2005-322659
However, the structure shown in FIGS. 1A and 1B and FIGS. 2A and 2B has the following problems.
FIGS. 3A and 3B are diagrams for illustrating problems of the conventional semiconductor device 10 shown in FIGS. 1A and 1B. FIG. 3A is a cross-sectional view of the semiconductor device 10, and FIG. 3B is an enlarged view of the part circled with a dotted line in FIG. 3A.
Referring to FIG. 3, the via filling resin 12, with which the vias 13 of the wiring board 1 are filled, has a coefficient of thermal expansion of 36×10−6 through 48×10−6/° C., which is greater than the coefficient of thermal expansion of the sealing resin 6 (13×10−6 through 16×10−6/° C.) or the coefficient of thermal expansion of copper (Cu) forming the wiring layers 8A and 8B of the wiring board 1 (16×10−6/° C.).
Accordingly, the via filling resin 12 with which the vias 13 are filled expands in the assembling time of the semiconductor device 10 or its heating process for packaging, and contracts after cooling. Therefore, stress concentrates on the periphery of the vias 13 of the wiring board 1 because of the differences in the coefficient of thermal expansion among the above-described materials when the temperature is high.
At this point, the adhesion between the sealing resin 6 and the resist layer 9A is reduced by the expansion or dehumidification of the wiring board 1, which has absorbed moisture when left in a predetermined atmosphere, at the interface part where the sealing resin 6 and the resist layer 9A selectively covering the wiring layer 8A of the wiring board 1 adhere to each other.
Further, the stress concentrating on the periphery of the vias 13 of the wiring board 1 becomes greater than the adhesion of the sealing resin 6 to the resist layer 9A, so that the adhesion between the sealing resin 6 and the resist layer 9A cannot be maintained. As a result, as shown in FIGS. 3A and 3B, the separation of the sealing resin 6 occurs at the interface between the resist layer 9A and the sealing resin 6 above the vias 13, so that air gaps (indicated by arrows A in FIGS. 3A and 3B) are formed in the sealing resin 6 at the interface (above the vias 13).
Further, in the conventional semiconductor device 10 shown in FIGS. 1A and 1B, only the part on the upper side of the wiring board 1 is sealed with the sealing resin 6, so that the semiconductor device 10 has a two-layer structure formed of the via filling resin 12 provided inside the wiring board 1 and the sealing resin 6 provided on the wiring board 1 and containing the semiconductor element 2, etc. Since the materials forming the semiconductor device 10 have different physical property values, there may be a large warp caused in the semiconductor device 10.
Such a warp of the semiconductor device 10 causes the vertical positions of the solder balls 4 to be different when the semiconductor device 10 is mounted on a motherboard. As a result, no connection can be established to the motherboard with the solder balls 4 that are positioned vertically high, and a short circuit may be caused between terminals with the solder balls 4 that are positioned vertically low.